The UCIe-A 64GT/s PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between dies in advanced packaging environments. Leveraging the UCIe (Universal Chiplet Interconnect Express) 3.0 standard, this IP supports a blistering data rate of up to 64Gbps per lane, enabling next-generation AI, HPC, and data center SoC applications.

Key Features

• Data Rate: Up to 64GT/s per lane

• Power Efficiency: 0.20 ~ 0.40 pJ/bit (process dependent)

• Beachfront and Area per x64 module

  • Bump Pitch: 45um

  • Beachfront Bandwidth: ~388.8um

  • Area: < 0.7mm²

• Supports various types of Advanced Packages

• x64 Transmission and x64 Receiving Lanes per module

• Supports @speed Manufacture Tests for both CP and FT with built-in programmable test patterns generator: PRBS7, PRBS23, or user-defined

• Supports broadcast register write to shorten programming time

• Per-bit real-time data eye monitor provides comprehensive insight into data transmission

• Firmware-based calibration and training allow fast product and system turnaround time Supports 3D packages (UCIe v2.0)

• Low Latency: Sub-nanosecond latency for critical computing applications

• Robust Signal Integrity: Designed for high-performance computing environments with challenging noise and crosstalk conditions

• Beachfront Bandwidth per 1.0mm

  • 165 GB/s @4GT/s

  • 329 GB/s @8GT/s

  • 494 GB/s @12GT/s

  • 658 GB/s @16GT/s

  • 988 GB/s @24GT/s

  • 1,316 GB/s @32GT/s

  • 1,976 GB/s @48GT/s

  • 2,632 GB/s @64GT/s

• Fully integrated solution with IPT UCIe Controller

• Supports IO bypass mode for easy system integration and user-defined applications