Our LPDDR5X PHY is a cutting-edge, high-performance physical layer interface PHY designed to meet the demanding requirements of modern computing and mobile applications. This PHY supports the latest LPDDR5X standard, providing enhanced data rates, lower latency, and improved power efficiency. It is ideal for applications such as smartphones, tablets, laptops, and high-performance computing systems, where speed and energy efficiency are paramount.

Key Features

l  Supports High Data Rate

o    8,533 MT/s (5nm and 3nm)

o    6,400 MT/s (16nm and 12nm)

l  Compliant with JEDEC LPDDR5X standards

l  Scalable Architecture: Supports multiple channels and ranks, offering flexibility for various memory configurations.

l  Supports all auto calibrations:

o    Impedance calibration

o    Delay measurement for clock period

o    Write-leveling and gate training (per DRAM specification)

o    Read and Write data eye training

o    Per-bit, per-rank delay controllable (including CA/DQ/DQS)

o    Etc.

l  Industry leading area and power

l  Robust Signal Integrity: Advanced equalization and timing features to ensure reliable data transmission.

l  Supports I/O with power-down retention

l  Supports CA and DQ signal swap table for easy system integration

l  Supports Dynamic Voltage  and Frequency Scaling (DVFS)

l  Compliant with AMBA APB3.0 for register accessing