Our DDR and LPDDR Combo PHY is a versatile and high-performance solution designed to meet the memory interface needs of modern computing systems. This multi-standard PHY supports different types of DDR and LPDDR, providing flexibility and future-proofing for various applications including high-performance computing, mobile devices, and data centers. It ensures robust performance with high data rates, low latency, and efficient power consumption.

Key Features

l  Supports multiple combinations of DDR/LPDDR interfaces

o    DDR3, DDR3L, DDR4 and LPDDR4 combo PHY

o    LPDDR4X and LPDDR5 combo PHY

o    LPDDR5 and LPDDR5X combo PHY

o    DDR4, DDR5 and LPDDR4 combo PHY

o    DDR4, DDR5, LPDDR4, LPDDR4X combo PHY

o    Etc.

l  Compliant with JEDEC DDR and LPDDR standards

l  Supports all auto calibrations:

o    Impedance calibration

o    Delay measurement for clock period

o    Write-leveling and gate training (per DRAM specification)

o    Read and Write data eye training

o    Per-bit, per-rank delay controllable (including CA/DQ/DQS)

o    Etc.

l  Industry leading area and power

l  Robust Signal Integrity: Advanced equalization and timing features to ensure reliable data transmission.

l  Supports DDR/LPDDR I/O with power-down retention

l  Supports CA and DQ signal swap table for easy system integration

l  Supports LPDDR Dynamic Voltage  and Frequency Scaling (DVFS)

l  Compliant with AMBA APB3.0 for register accessing