產品介紹
程萬里 眾目具
D2D (Chiplet 2 chiplet ) PHY

Double data rate (DDR) architecture

Silicon proven Q3, 2022 @16Gbps in advance node.

Special high-speed standard cells @10G

Special high-speed IO @20G (CoWoSTM)

Data eye monitors with left/right guards (PVT sensor)

Patent pending VT adaptive receiver

Short porting time to other process

Customer feedbacks

BER = 0 over long period of time (amazing)

Firmware base design allow easy update

“Partner” award from customer

Mass production taped out December 2022



 

聯絡我們
Contact Us